1. Field of the Invention
The present invention relates to a deformable mirror device (DMD), and more specifically, the present invention relates to a method of driving a DMD.
2. Description of the Related Art
The development of high intensity, high definition flat panel displays (FPDs) has been advancing in recent years. Displays such as liquid crystal displays, EL (electroluminescence) displays, and plasma displays can be given as examples of FPDs.
Furthermore, in addition to the above FPDs, digital micromirror devices (hereafter referred to as DMDs) have been in the spotlight. Techniques related to DMDs have been disclosed by Texas Instruments, Inc., in patent applications such as: Japanese Patent Application Laid-open No. Hei 5-150173, Japanese Patent Application Laid-open No. Hei 5-183851, Japanese Patent Application Laid-open No. Hei 7-240891, Japanese Patent Application Laid-open No. Hei 8-334709, Japanese Patent Application Laid-open No. Hei 8-227044, Japanese Patent Application Laid-open No. Hei 8-051586, and Japanese Patent Application Laid-open No. Hei 8-227044.
A plurality of micromirrors approximately 16 xcexcmxc3x9716 xcexcm in size are formed having a pitch of 17 mxcexc on a CMOS SRAM formed on a silicon substrate, and each of the micromirrors corresponds to a screen pixel, in the DMD. The number of micromirrors reaches 480,000 for SVGA, 786,000 for XGA, and 1,300,000 for SXGA.
The angle of the micromirror changes by an angle xcex8 with respect to the substrate if a digital signal having image information (digital video signal) is input to the SRAM of the DMD, in accordance with an electric field effect due to voltage from the SRAM. If the angle of the micromirror with respect to the substrate changes by an amount xcex8 (where 0 less than xcex8 less than 90xc2x0), then light from a light source is separated into two directions when reflected in the micromirror. One of the lights separated into two directions is absorbed by a light absorber, while the other arrives at a screen and forms an image.
Note that the term digital signal denotes a signal having two voltage valuesin this specification. Of the two voltage values, the higher is indicated by the term HI, while the lower is indicated by the term LO.
Schematic diagrams of a structure of a general DMD pixel are shown in FIGS. 20A and 20B. FIG. 20A is a perspective diagram of a DMD pixel, and FIG. 20B is a cross sectional diagram of the DMD pixel of FIG. 20A. A plurality of pixels are formed on a substrate 901, and each pixel has a first electrode (first address electrode) 902a, a second electrode (second address electrode) 902b, landing sites 903, a micromirror 904, a hinge 905, and hinge support posts 906.
The angle of the micromirror 904 with respect to the substrate 901 is changed by an amount xcex8 with the hinge 905 acting as a rotational axis. Thehinge 905 is fixed on the substrate 901 by the hinge posts 906.
A portion of the micromirror 904 contacts the landing site 903 when the micromirror 904 is inclined to an angle greater than xcex8 with respect to thesubstrate with the hinge 905 as an axis of rotation. The landing site 903 is maintained at the same electric potential as that of the mirror 904, or has insulating properties.
The electric potential of a digital video signal input to the pixel is imparted to the first address electrode 902a. Further, the digital video signal is inverted with electric potential of ground as a standard point, and the inverted signal is imparted to the second address electrode 902b as an inverted digital video signal.
A fixed electric potential (standard electric potential) is imparted to the micromirror 904. The micromirror 904 is then inclined by an angle xcex8 to thefirst address electrode 902a side if the electric potential difference between the standard electric potential and that of the digital video signal is greater than the size of the electric potential difference between the standard electric potential and that of the inverted digital video signal. Conversely, if the electric potential difference between the standard electric potential and that of the digital video signal is smaller than the size of the electric potential difference between the standard electric potential and that of the inverted digital video signal, then the micromirror 904 is inclined by an angle xcex8 to the second address electrode 902b side.
Digital light processing (DLP) with a projector using a DMD having the above structure differs from a projector using liquid crystals, and there is no light loss from a polarizing plate, and the aperture ratio is equal to or greater than 90%; the efficiency of utilizing light is therefore high. Further, this is a reflective type device, differing from general transmission type liquid crystal panels, and therefore the spacing between pixels, namely the spacing between the micromirrors, is small at about 0.8 xcexcm, and a high definition image can easily be obtained even a projection is enlarged on the screen. In addition, no thermal problem develops like that of liquid crystal panels using thin film transistors because DMDs have superior cooling efficiency, and it is possible to use a high power light source, and therefore making projectors high definition becomes easy.
A drive circuit of a pixel in a conventional DMD is shown next in FIG. 21. Reference numeral 911 denotes a data driver, reference numeral 912 denotes a scanning driver, and reference numeral 914 denotes a pixel portion. The pixel portion 914 has a plurality of pixels 913.
The digital driver 911 inputs a digital video signal into a plurality of data lines 918, and the scanning driver 912 inputs a scanning signal into a plurality of scanning lines 917. Regions having one data line 918 and one scanning line 917 correspond to the pixels 913 for the case of the DMD shown by FIG. 21.
The pixels 913 each have a switching transistor 915, a SRAM 916 having a plurality of transistors. A gate electrode of the switching transistor 915 is connected to the scanning line 917. Further, one of a source region and a drain region of the switching transistor 915 is connected to the data line 918, and the other is connected to an input terminal Vin of the SRAM 916 and to the first address electrode 902a. 
Note that the term SRAM denotes a static RAM having no transfer gates throughout this specification. If HI input is imparted to the SRAM, then LO output is obtained, and if LO input is imparted to the SRAM, then HI output is obtained. Conversely, if a HI output is imparted to the SRAM, then a LO input is obtained, and if a LO output is imparted to the SRAM, then a HI input is obtained.
Note that, throughout this specification, the term transistor denotes an electric field effect transistor, which functions as a switching element.
An out put terminal Vout of the SRAM 916 is connected to the second address electrode 902b. Further, Vddh denotes a high voltage side electric power source, and Vss denotes a low voltage side electric power source.
The switching transistor 915 is selected in the DMD shown in FIG. 21 by the scanning signal input to the scanning line 917 from the scanning driver 912. Note that, in this specification, the term selection of a wiring denotes a state in which all transistors whose gate electrode is connected to the wiring are on.
The digital video signal is then input to the data line 918 from the data driver 911. The input digital video signal is input to the input terminal Vin of the SRAM 916, and to the first address electrode 902a, through the switching transistor 915 in an ON state. The digital video signal input to the input terminal Vin of the SRAM 916 is inverted, with the ground electric potential as a standard, and is then output from the output terminal Vout as an inverted digital video signal, and input to the second address electrode 902b. 
If the digital video signal and the inverted digital video signal are input to the first address electrode 902a and to the second address electrode 902b, respectively, then the angle of the micromirror 904 of the pixel with respect to the substrate is selected in accordance with the 1xe2x80x3 or 0xe2x80x3 information of the digital video signal. Whether light from a light source is irradiated to a screen, or is irradiated to a light absorber, is selected when the angle with respect to the substrate is selected.
The digital video signal is then input in order to all of the pixels 913 of the pixel portion 914, and the micromirror angles are selected. Note that, in this specification, the term digital video signal input to the pixels 913 refers to the digital video signal being input to the source region or the drain region of the switching transistors 915 of the pixels 913.
If the digital video signal is then once again input to the same pixels, the micromirror angles are selected again.
Time division gray scale display of a conventional DMD is explained next using FIG. 22. The horizontal axis shows a time scale, and the vertical axis shows the position of a scanning line in FIG. 22.
A plurality of subframe periods are formed in one frame period with the time division gray scale display used by conventional DMDs.
An example in which n subframe periods are formed within one frame period is shown in FIG. 22. By then selecting the angle of the micromirror in each of the n subframe periods in accordance with the digital video signal, light from the light source is irradiated to the screen or to the light absorber. Hereafter, light irradiated to the screen is referred to as white display, and light irradiated to the light absorber is referred to as black display.
White display or black display is selected from the first subframe to the number n subframe in accordance with the first bit to the number n bit of the digital video signal.
By selecting white display or black display in the n subframe periods, the length of the white display periods and the length of the black display periodswithin one frame period can be controlled. As a result, the gray scale of an image formed by one frame period can be controlled.
However, if the number of gray scales of the image displayed is increased with the conventional DMD time division gray scale display shown in FIG. 22, the length of the subframe periods becomes shorter. A problem therefore develops in that the write in speed of the digital video signal to the pixels cannot be managed. This problem is explained in detail below using FIG. 23.
The horizontal axis of FIG. 23 shows a time scale, and the vertical axis shows the position of a scanning line. Further, reference symbol t1 denotes the length of a period for writing in the number i bit of the digital video signal to the pixel, and reference symbol t2 denotes the length of a subframe period SFi.
For the case of the drive shown in FIG. 23, t1 t2, and the number i bit of the digital video signal is written into all of the pixels before the number i subframe period SFi is complete and the number (i+1) subframe period SF(i+1) begins. Write in of the number i bit of the digital video signal to the pixels and write in of the number (i+1) bit of the digital video signal to the pixels are therefore not performed in parallel within the same pixel portion.
However, if the number of gray scales becomes larger, and the number i subframe period SFi becomes shorter, then t1 greater than t2. In this case, there are times when write in of the number i bit of the digital video signal to the pixels is not complete, even though the number i subframe period SFi is finished. In other words, write in of the number (i+1) bit of the digital video signal to the pixels must be performed in parallel with write in of the number i bit of the digital video signal. With the DMD structure shown by FIG. 21, drive in which t1 greater than t2 is impossible.
In view of the above problem, an object of the present invention is to provide a DMD having a novel structure in which display of an image at a high number of gray scales is possible.
The inventors of the present invention proposed a first structure in which two switching elements having their gate electrodes connected to differing scanning lines (a switching transistor and an erasure transistor) are formed in each pixel, and in which switching is controlled separately.
A digital video signal is input to a pixel by placing the switching transistor in an ON state, and a state of black display in the pixel is set by placing the erasure transistor in an ON state. Switching of the switching transistor and the erasure transistor is controlled by using separate scanning driver circuits. Input of the digital video signal in order to the pixels can therefore be performed, in the same pixel portion, in parallel with the setting of a black display state in order in the pixels.
A method of driving a DMD of the present invention is explained using FIG. 1. The horizontal axis shows a time scale in FIG. 1, while the vertical axis shows the position of a scanning line. Further, reference symbol t1 denotes the length of a display period Tri in which each line of pixels performs display in accordance with the number i bit of the digital video signal, and reference numeral t2 denotes the length of a period for performing write in of the number i bit of the digital video signal into all of the pixels.
With the method of driving of FIG. 1, the display period Tri begins by placing the switching transistors into an ON state and writing the number i bit of the digital video signal into the pixels.
Next, the pixels become placed in a black display state, in order, after the display period Tri begins and through the time t1 by turning on the erasure transistors, and the display period Tri is complete. Note that, in this specification, the period during which the pixels are placed in a black display state by turning on the erasure transistors is referred to as a non-display period Td. In particular, the non-display period appearing directly after the display period Tri is referred to as Tdi.
Reference symbol t3 denotes the length of the non-display period Tdi in each line of pixels. It is very important that the length t3 of the non-display period be such that the period for performing write in of the number i bit of the digital video signal to the pixels, and the period for performing write in of the number (i+1) bit of the digital video signal to the pixels, do not overlap. That is, it is very important that t3xe2x89xa7t2 xe2x88x92t1.
The switching transistors again become placed in an ON state after passing the time t3 from the start of the non-display period Tdi, and write in of the number (i+1) bit of the digital video signal to the pixels begins. The non-display period Tdi is completed at the same time as the beginning of write in period of the number (i+1) bit of the digital video signal to the pixels, and the display period Tr(i+1) begins.
In accordance with the above driving method, it becomes possible to make the length of the display period Tri shorter than the length of the period for write in of the digital video signal to all of the pixels, even if write-in to the pixels of the number i bit of the digital signal and write-in to the pixels of the number (i+1) bit of the digital signal are not performed in parallel.
In other words, compared to the time division gray scale display of a conventional DMD, it becomes possible to make the length of the display period corresponding to a conventional subframe period shorter with the DMD time division gray scale display of the first structure of the present invention. Consequently, even if the write in speed to the pixels of the digital video signal is the same as the conventional speed, it becomes possible to make the number of image gray scale very large.
Further, the inventors of the present invention proposed a second structure in which two switching elements having their gate electrodes connected to differing scanning lines (a first switching transistor and a second switching transistor) are formed in each pixel, and in which switching is controlled separately. In the second structure, the two switching transistors are referred to as the first switching transistor and the second switching transistor in the second structure, and both are referred to using the generic name switching transistors.
Input of the number i bit of a digital video signal to the pixels can be performed in parallel with input of the number (i+1) bit of the digital video signal to the pixels, in the same pixel portion, by controlling the first switching transistor and the second switching transistor separately.
A method of driving of the present invention is explained using FIG. 2. The horizontal axis shows a time scale in FIG. 2, while the vertical axis shows the position of a scanning line. Further, reference symbol t1 denotes the length of a period for performing write in of the number i bit of the digital video signal into all of the pixels, and reference symbol t2 denotes the length of a display period Tri in which each line of pixels performs display in accordance with the number i bit of the digital video signal. Case in which t1 greater than t2 is shown in FIG. 2.
With the method of driving of FIG. 2, the display period Tri begins by placing the first switching transistors into an ON state and writing the number i bit of the digital video signal into the pixels.
Next, the number (i+1) bit of the digital video signal is written into the pixels, in order, after the display period Tri begins and up through the time t2 by placing the second switching transistors in an ON state. The display period Tri is completed, and the display period Tr(i+1) begins, in order, from the pixels into which the number (i+1) bit of the digital video signal is written.
It becomes possible to perform write-in to the pixels of the number i bit of the digital video signal, and the number (i+1) bit of the digital video signal, in parallel by using the above driving method. It also becomes possible to make the display period Tri shorter than the length of the period for writing in the digital video signal to all of the pixels.
Compared to the time division gray scale display of a conventional DMD, it becomes possible to make the length of the display period corresponding to a conventional subframe period be shorter with the DMD time division gray scale display of the second structure of the present invention. Consequently, even if the write in speed to the pixels of the digital video signal is the same as the conventional speed, it becomes possible to make the number of image gray scale very large.
Now, the structure of the present invention will be described.
According to a first structure of the present invention, there is provided a micromirror device comprising a data driver, a write in scanning driver, an erasure scanning driver, a pixel portion, and a power source for the erasing operation, characterized in that:
the pixel portion has a plurality of pixels;
each one of the plurality of pixels has a first address electrode and a second address electrode;
a digital video signal output from the data driver is input to the first address electrode by the write in scanning driver;
an electric potential of the power source for the erasing operation is applied to the second address electrode by the erasure scanning driver;
the electric potential of the first address electrode and the electric potential of the second address electrode are always inverted with ground taken as a reference point.
The present invention relates to a micromirror device comprising a data driver, a write in scanning driver, an erasure scanning driver, a pixel portion, and a power source for the erasing operation, characterized in that:
the pixel portion has a plurality of pixels;
each one of the plurality of pixels has a switching transistor, an SRAM, a transistor for the erasing operation, a first address electrode and a second address electrode;
the write in scanning driver controls a switching of the switching transistor;
the erasure scanning driver controls a switching of the transistor for the erasing operation;
the data driver inputs a digital video signal to an input terminal of the SRAM and to the first address electrode through the switching transistor;
an output terminal of the SRAM is connected to the second address electrode; and
the power source for the erasing operation is connected to the second address electrode and the output terminal through the transistor for the erasing operation.
According to the first structure of the present invention, there is provided a micromirror device comprising a data driver, a write in scanning driver, an erasure scanning driver, a pixel portion, and a power source for the erasing operation, a plurality of scanning lines for the writing operation, and a plurality of scanning lines for the erasing operation, characterized in that:
the pixel portion has a plurality of pixels;
each one of the plurality of pixels has a switching transistor, a SRAM, a transistor for the erasing operation, a first address electrode and a second address electrode;
a switching of the switching transistor is controlled by a scanning signal for the writing operation which is input to the plurality of the scanning lines for the writing operation from the write in scanning driver;
a switching of the transistor for the erasing operation is controlled by a scanning signal for the writing operation which is input to the plurality of the scanning lines for the erasing operation from the erasure scanning driver;
the data driver inputs a digital video signal to an input terminal of the SRAM and to the first address electrode through the switching transistor;
an output terminal of the SRAM is connected to the second address electrode; and
the power source for erasing operation is connected to the second address electrode and the output terminal through the transistor for erasing operation.
According to the first structure of the present invention, there is provided a micromirror device comprising a data driver, a write in scanning driver, an erasure scanning driver, a pixel portion, and a power source for the erasing operation, characterized in that:
the pixel portion has a plurality of pixels;
each one of the plurality of pixels has a first address electrode and a second address electrode;
a digital video signal output from the data driver is input to the first address electrode by the write in scanning driver;
an electric potential of the power source for the erasing operation is applied to the second address electrode by the erasure scanning driver;
the electric potential of the first address electrode and the electric potential of the second address electrode are always inverted with ground taken as a reference point;
n display periods Tr1, Tr2 . . . and Trn and j non-display periods Td1, Td2,and Tdj appear within one frame period of each line of pixels of the plurality of pixels;
a display period Tri (i is 1, . . . or any one of n) is a period from when the number i bit of a digital video signal is input to each line of the pixels, until the next digital video signal is input to each line of the pixels, or a period until the electric potential of the power source for the erasing operation is applied to the second address electrodes which are possessed by each line of the pixels, respectively;
a non-display period Tdk (k is 1, . . . or any one of n) is a period from when the electric potential of the power source for the erasing operation is applied to the second address electrodes which are possessed by each line of the pixels, respectively, until the digital video signal is input to each line of the pixels;
after all of the n display periods Tr1, Tr2, . . . , and Trn appeared, any one of the n display periods Tr1, Tr2, . . . , and Trn appears again;
white display or black display is selected, by the digital video signal, in the n display periods Tr1, Tr2, . . . , and Trn; and
the ratio of lengths of the n display periods Tr1, Tr2, . . . , and Trn is represent by 20::21::22 . . . , 2(nxe2x88x921).
According to the first structure of the present invention, there is provided a micromirror device comprising a data driver, a write in scanning driver, an erasure scanning driver, a pixel portion, and a power source for the erasing operation, a plurality of scanning lines for the writing operation, and a plurality of scanning lines for the erasing operation, characterized in that:
the pixel portion has a plurality of pixels;
each one of the plurality of pixels has a switching transistor, a SRAM, a transistor for the erasing operation, a first address electrode and a second address electrode;
the write in scanning driver controls a switching of the switching transistor;
the erasure scan driver controls a switching of the transistor for the erasing operation;
the data driver inputs a digital signal to an input terminal of the SRAM and to the first address electrode through the switching transistor;
an output terminal of the SRAM is connected to the second address electrode;
the power source for the erasing operation is connected to the second address electrode and to the output terminal through the transistor for the erasing operation;
n display periods Tr1, Tr2 . . . and Trn and j non-display periods Td1, Td2,and Tdj appear within one frame period of each line of pixels of the plurality of pixels;
a display period Tri (i is 1, . . . or any one of n) is a period from when the number i bit of a digital video signal is input to each line of the pixels, until the next digital video signal is input to each line of the pixels, or a period until the electric potential of the power source for the erasing operation is applied to the second address electrodes which are possessed by each line of the pixels, respectively;
a non-display period Tdk (k is 1, . . . or any one of n) is a period from when the electric potential of the power source for the erasing operation is applied to the second address electrodes which are possessed by each line of the pixels, respectively, until the digital video signal is input to each line of the pixels;
after all of the n display periods Tr1, Tr2, . . . and Trn appeared, any one of the n display periods Tr1, Tr2, . . . , and Trn appears again;
white display or black display is selected, by the digital video signal, in the n display periods Tr1, Tr2, . . . , and Trn; and
the ratio of lengths of the n display periods Tr1, Tr2, . . . , and Trn is represent by 20::21::22 . . . , 2(nxe2x88x921).
According to the first structure of the present invention, there is provided a driving method of a micromirror device comprising a pixel portion and a power source for the erasing operation, characterized in that:
the pixel portion has a plurality of pixels;
each one of the plurality of pixels has a first address electrode and a second address electrode;
n display periods Tr1, Tr2 . . . and Trn and j non-display periods Td1, Td2,and Tdj appear within one frame period of each line of pixels of the plurality of pixels;
a display period Tri (i is 1, . . . or any one of n) is a period from when the number i bit of a digital video signal is input to each line of the pixels, until the next digital video signal is input to each line of the pixels, or a period until the electric potential of the power source for the erasing operation is applied to the second address electrodes which are possessed by each line of the pixels, respectively;
a non-display period Tdk (k is 1, . . . or any one of n) is a period from when the electric potential of the power source for the erasing operation is applied to the second address electrodes which are possessed by each line of the pixels, respectively, until the digital video signal is input to each line of the pixels;
after all of the n display periods Tr1, Tr2, . . . , and Trn appeared, any one of the n display periods Tr1, Tr2, . . . , and Trn appears again;
white display or black display is selected, by the digital video signal, in the n display periods Tr1, Tr2, . . . , and Trn; and
the ratio of lengths of the n display periods Tr1, Tr2, . . . , and Trn is represent by 20::21::22. . . , 2(nxe2x88x921).
The first structure of the present invention may have a feature that the plurality of pixels each have a micromirror.
The first structure of the present invention may have a feature that white display or black display is selected, by the digital video signal, in the n display periods Tr1, Tr2, . . . , and Trn.
The first structure of the present invention may have a feature that when the electric potential of the power source for the erasing operation is applied to the second address electrode, the micromirror is tilted in a direction so that black display is performed.
The first structure of the present invention may have a feature that the SRAM has two p-channel transistors and two n-channel transistors.
The first structure of the present invention may have a feature that the SRAM has two p-channel transistors and two resistors.
The first structure of the present invention may have a feature that the SRAM has two n-channel transistors and two resistors.
The first structure of the present invention includes a projector which is characterized by having the micromirror device.
According to a second structure of the present invention, there is provided a micromirrror device comprising a first data driver, a second data driver, a scanning driver, and a pixel portion, characterized in that:
the pixel portion has a plurality of pixels;
each of the plurality of pixels has a first switching transistor, a second switching transistor, a SRAM, a first address electrode, and a second address electrode;
the scanning driver controls a switching of the first switching transistor and a switching of the second switching transistor;
the first data driver inputs a digital signal to an input terminal of the SRAM and to the first address electrode through the first switching transistor;
the second data driver inputs a digital signal to an output terminal of the SRAM and the second address electrode through the second switching transistor;
the digital signal input to the input terminal is inverted, with an electricpotential of a ground being a reference, to be output from the output terminal; and
the digital signal input to the output terminal is inverted, with the electric potential of the ground being the reference, to be output from the input terminal.
According to the second structure of the present invention, there is provided a micromirror device comprising a first data driver, a second data driver, a scanning driver, a plurality of first scanning lines, a plurality of second scanning lines, a plurality of a first data lines, and a plurality of a second data lines, characterized in that:
the pixel portion has a plurality of pixels;
each of the plurality of pixels has a first switching transistor, a second switching transistor, a SRAM, a first address electrode, and a second address electrode;
a switching of the first switching transistor and a switching of the second switching transistor are controlled by scanning signals input from the scanning driver to the plurality of the first scanning lines and the plurality of the second scanning lines;
a digital signal input from the first data driver to the plurality of the first data lines, is input to an input terminal of the SRAM and to the first address electrode through the first switching transistor;
a digital signal input from the second data driver to the plurality of the second data lines, is input to an output terminal of the SRAM and to the second address electrode through the second switching transistor;
the digital signal input to the input terminal is inverted, with an electric potential of a ground being a reference, to be output from the output terminal; and
the digital signal input to the output terminal is inverted, with the electric potential of the ground being the reference, to be output from the input terminal.
According to the second structure of the present invention, there is provided a micromirror device comprising a first data driver, a second data driver, a scan driver, and a pixel portion, characterized in that:
the pixel portion has a plurality of pixels;
each of the plurality of pixels has a first switching transistor, a second switching transistor, a SRAM, a first address electrode, and a second address electrode;
the scan driver controls a switching of the first switching transistor and a switching of the second switching transistor;
the first data driver inputs a digital signal to an input terminal of the SRAM and the first address electrode through the first switching transistor;
the second data driver inputs a digital signal to an output terminal of the SRAM and the second address electrode through the second switching transistor;
the digital signal input to the input terminal is inverted, with an electric potential of a ground being a reference, to be output from the output terminal; and
the digital signal input to the output terminal is inverted, with the electric potential of the ground being the reference, to be output from the input terminal;
(n+j) display periods Tr1, Tr2 . . . and Tr(n+j) appear in order within one frame period of each line of pixels of the plurality of pixels;
among the (n+j) display periods Tr1, Tr2 . . . and Tr(n+j), j display period is a non-display period;
among the (n+j) display periods Tr1, Tr2 . . . and Tr(n+j), white display or black display is selected by the digital signal within a display period, which is not the non-display period;
after all of the (n+j) display periods Tr1, Tr2, . . . , and Tr(n+j) appeared, the (n+j) display periods Tr1, Tr2, . . . , and Tr(n+j) appears, in order, again; and
among the (n+j) display periods Tr1, Tr2 . . . and Tr(n+j), the ratio of lengths of the display periods, which are not the non-display periods, are arranged in order from the shortest, is represent by 20::21::22. . . , 2(nxe2x88x92n).
According to the second structure of the present invention, there is provided a micromirror device comprising a first data driver, a second data driver, a scanning driver, a plurality of first scanning lines, a plurality of second scanning lines, a plurality of a first data lines, and a plurality of a second data lines, characterized in that:
the pixel portion has a plurality of pixels;
each of the plurality of pixels has a first switching transistor, a second switching transistor, a SRAM, a first address electrode, and a second address electrode;
a switching of the first switching transistor and a switching of the second switching transistor are controlled by scanning signals input from the scanningdriver to the plurality of the first scanning lines and to the plurality of the second scanning lines;
a digital signal input from the first data driver to the plurality of the first data lines, is input to an input terminal of the SRAM and to the first address electrode through the first switching transistor;
a digital signal input from the second data driver to the plurality of the second data lines, is input to an output terminal of the SRAM and to the secondaddress electrode through the second switching transistor;
the digital signal input to the input terminal is inverted, with an electricpotential of a ground being a reference, to be output from the output terminal;
the digital signal input to the output terminal is inverted, with the electric potential of the ground being the reference, to be output from the input terminal;
(n+j) display periods Tr1, Tr2 . . . and Tr(n+j) appear in order within one frame period of each line of pixels of the plurality of pixels;
among the (n+j) display periods Tr1, Tr2 . . . and Tr(n+j), j display period is a non-display period;
among the (n+j) display periods Tr1, Tr2 . . . and Tr(n+j), white display or black display is selected by the digital signal within a display period, which is not the non-display period;
after all of the (n+j) display periods Tr1, Tr2, . . . , and Tr(n+j) appeared, the (n+j) display periods Tr1, Tr2, . . . , and Tr(n+j) appears, in order, again; and
among the (n+j) display periods Tr1, Tr2 . . . and Tr(n+j), the ratio of lengths of the display periods, which are not the non-display periods, are arranged in order from the shortest, is represent by 20::21::22 . . . , 2(nxe2x88x921).
According to the second structure of the present invention, there is provided a driving method of a micromirror device having a pixel portion, characterized in that:
the pixel portion has a plurality of pixels;
each of the plurality of the pixels has a first address electrode and a second address electrode;
(n+j) display periods Tr1, Tr2 . . . and Tr(n+j) appear in order within one frame period of each line of pixels of the plurality of pixels;
among the (n+j) display periods Tr1, Tr2 . . . and Tr(n+j), j display period is a non-display period;
among the (n+j) display periods Tr1, Tr2 . . . and Tr(n+j), white display or black display is selected by the digital signal within a display period, which is not the non-display period;
after all of the (n+j) display periods Tr1, Tr2, . . . , and Tr(n+j) appeared, the (n+j) display periods Tr1, Tr2, . . . , and Tr(n+j) appears, in order, again; and
among the (n+j) display periods Tr1, Tr2 . . . and Tr(n+j), the ratio of lengths of the display periods, which are not the non-display periods, are arranged in order from the shortest, is represent by 20::21::22 . . . , 2(nxe2x88x921).
The second structure of the present invention may have a feature that the (n+j) display periods Tr1, Tr2, . . . , and Tr(n+j) are periods from when the digital signal is written to the pixels in the (n+j) write in periods Ta1, Ta2, . . . , and Ta (n+j), until the digital signal is input to the pixels in the write in period which appears next to the (n+j) write in periods Ta1, Ta2, . . . , and Ta(n+j).
The second structure of the present invention may have a feature that among the (n+j) write in periods Ta1, Ta2, . . . , and Ta (n+j), an arbitrary write in period Tai does not overlap with a write in period which appears before two write in periods of the arbitrary write in period Tai and with a write in period which appears after two write in periods of the arbitrary write in period Tai.
The second structure of the present invention may have a feature that the plurality of pixels each have a micromirror.
The second structure of the present invention may have a feature that the SRAM has two p-channel transistors and two n-channel transistors.
The second structure of the present invention may have a feature that the SRAM has two p-channel transistors and two resistors.
The second structure of the present invention may have a feature that the SRAM has two n-channel transistors and two resistors.
The second structure of the present invention includes a projector which is characterized by having the micromirror device.